MIT Assistant Professor Max Shulaker showed a 3DIC wafer with carbon nanotubes + RRAM stacked by ILV technology at the DARPA Electronic Revival Initiative (ERI) Summit. The special significance of this wafer is that it is the first time that carbon nanotube + RRAM + ILV 3DIC technology has been formally processed by a third-party foundry (SkyWater Technology Foundry), which represents that carbon nanotube + RRAM + ILV 3DIC is officially out of school The laboratory is moving towards commercialization and large-scale application.
Carbon Nanotubes + RRAM + ILV 3DIC Origin
Let's start with 3DIC. As Moore's Law is gradually approaching the bottleneck, it has become more and more difficult to achieve the improvement of chip performance by shrinking the semiconductor process. To solve this problem, the semiconductor industry has proposed the use of advanced packaging and heterogeneous computing methods to continue to improve chip system performance. Traditional general-purpose chips try to use a general-purpose processor to solve all application problems. Therefore, it is difficult to meet the needs of applications today when Moore's Law is approaching the failure of the processor, and the performance of the processor has slowed down. Block chips are tightly integrated in a package, and each chip is tailored for a specific application, so it can efficiently and targetedly process applications to meet the needs of application scenarios. 3DIC is one of such advanced packaging technologies. Using 3DIC can stack multiple chips together and use TSV technology to achieve high-speed and efficient data communication between chips. When 3DIC is used, the distance between the chips is short, the interconnection line density is large, and high-speed signal transmission can be achieved. Therefore, by packaging the processor chip and the memory chip together, high-speed processor-memory interconnection can be achieved, thereby solving memory The access bottleneck (memory wall) problem greatly improves the overall performance of the chip system.
Through the above analysis, we can see that the key to 3DIC is how to achieve high-density chip-to-chip interconnection, and this is also the main breakthrough of the main character of this article-carbon nanotube + RRAM + ILV 3DIC. In traditional TSV 3DIC, different chips are stacked together and TSV is used to achieve interconnection, and the pitch of TSV interconnect lines is about 10 microns. In contrast to TSV 3DIC, carbon nanotube + RRAM + ILV 3DIC does not manufacture multiple chips and stack them in packages, but directly implements multiple chips on a single wafer (single-chip 3DIC). How does this work? We know that the traditional chip manufacturing process is to first manufacture the active area, and then make multiple layers of metal interconnections above the active area. Each time a metal interconnection is completed, an insulating layer is deposited on top of it. A dielectric layer (inter-layer dielectric, ILD), and then a metal interconnection layer is grown again on the ILD layer, and so on until a dozen or more metal interconnections are completed.
At the same time, inter-layer interconnections can be implemented between different metal layers through metal inter-layer vias (ILVs). The implementation method of carbon nanotube + RRAM + ILV 3DIC is a bit similar to the traditional method of manufacturing metal interconnects on a chip: after the manufacture of the underlying standard CMOS active area is completed, not only the metal interconnects but also carbon nanotubes and RRAM, for example, Max Shulaker realized the NMOS active area-> ILD + ILV-> carbon nanotube layer-> ILD + ILV-> RRAM-> ILD + ILV-> carbon nanotube layer in the 2017 Nature paper. In this way, a multilayer transistor stack 3DIC can be realized on a wafer without the need for packaging technology. More importantly, the interconnection density of 3DIC using ILV technology is extremely large, which can easily reach tens of nanometers, thereby greatly improving the performance of the overall chip system.
Why use carbon nanotubes and RRAM? The reason is that in addition to the performance and energy efficiency of carbon nanotubes and RRAM beyond traditional CMOS transistors / Flash memory, the more important reason is that the temperature of the ILV process must be controlled within 400 degrees, otherwise the logic of other layers will be damaged. Carbon nanotubes and RRAM are compatible with low-temperature processes, so they can be perfectly combined with ILV. In contrast, traditional silicon CMOS processes require temperatures up to 1000 degrees, so they can only be used as the bottom layer in 3DIC.
Latest release at DARPA ERI summit
Max Shulaker, assistant professor of Massachusetts Institute of Technology, showed enthusiastic applause from the audience when he showed the carbon nanotube + RRAM + ILV 3DIC wafer at the DARPA ERI summit. As mentioned earlier, Shulaker has completed the prototype preparation of carbon nanotubes + RRAM + ILV 3DIC in the foundry of the laboratory in 2017 and published a Nature paper, and the wafers displayed this time are in carbon nanotubes + RRAM + ILV 3DIC was successfully prepared for the first time in a third-party Foundry (SkyWater Technology).
Professor Shulaker told hundreds of engineers in Detroit on Tuesday: "This wafer was made last Friday and it is the first monolithic 3DIC produced at Foundry." This carbon nanotube + RRAM + ILV 3DIC prepared by a third-party Foundry has been supported by DARPA's 3DSoC project. This project aims to make 3DIC technology a further breakthrough. The ultimate goal is to make the 3DIC system using 90nm semiconductor feature size and the current use Compared with the most advanced 7-nanometer process chip, it has 50 times performance advantage. The project is only about a year old, but at the end of its 3 to 5 years of operation, what DARPA wants to do is to make 50 million logic gate chips, 4 gigabytes of non-volatile memory, The interconnection density between the logic layers reaches 9 million interconnections per square millimeter, the total interconnection data rate reaches 50Tb / s, and the energy efficiency ratio of the interconnection reaches 2pJ / bit.
The 3DIC system demonstrated by Professor Shulaker on Tuesday cannot yet do all of this, but it is an important milestone. "We, together with Skywater Technology Foundry and other partners, have revolutionized the way we make this technology, transforming it from a technology that works only in our academic labs to a technology that can now be foundry in the United States," he said. Work in commercial manufacturing facilities of factories. "
Currently, the technology used by SkyWater Technology to produce carbon nanotubes + RRAM + ILV 3DIC is a 90-nanometer process. In the future, it is expected to achieve smaller feature sizes and higher performance. In addition, after the process yield reaches mass production standards, SkyWater will provide PDK. On this basis, Skywater will be able to build a business around the process of carbon nanotubes + RRAM + ILV 3DIC and license the technology to other foundries.
Will carbon nanotubes + RRAM + ILV 3DIC change the semiconductor industry?
Carbon nanotube + RRAM + ILV monolithic 3DIC can provide interconnection density much higher than TSV, thus bringing further performance breakthroughs to 3DIC. However, if carbon nanotubes + RRAM + ILV 3DIC are to enter mainstream applications, they need to cross several barriers in engineering.
The first is the integrated scale of carbon nanotubes. Currently, we have seen Stanford University complete a 2 million carbon nanotube transistor chip, but this scale is still too small compared to the current SoC. If carbon nanotubes want to enter the mainstream, they need to increase the integration scale by at least 100-1000 times, which also includes the improvement of yield during large-scale integration.
Second is the issue of design method and ecology. Carbon nanotubes require a specially designed standard cell library. In addition, EDA tools and processes will also need corresponding designs (such as DRC, etc.).
At least for now, carbon nanotubes + RRAM + ILV 3DIC is just an academic project, but this is why DARPA pushed for the project, because once the above engineering problems are solved and the ecology can be built, carbon nanotubes + RRAM + ILV 3DIC will likely be the key to next-generation semiconductor technology. At the same time, as the United States is gradually losing its leading position in the field of semiconductor technology, DARPA also hopes to use the carbon nanotube + RRAM + ILV 3DIC technology to restore the United States' competitiveness in the field of semiconductor technology.
For China's semiconductor industry, carbon nanotubes + RRAM + ILV 3DIC is an area worthy of attention. At present, whether carbon nanotubes + RRAM + ILV 3DIC can truly become the next-generation standard semiconductor process still has a lot of uncertain factors. Therefore, while paying due attention to encouraging colleges and companies to do some common sense exploration, it is also beneficial to reduce the semiconductor industry in China The risk of avoiding this technology once it has become mainstream in our country is to pull away. In fact, the research on carbon nanotubes in Chinese universities has achieved a lot of results, but it has not been able to truly integrate key technologies into a complete system like Shulaker and advance to commercialization. This is exactly what we semiconductor people need to work together to fill the vacancies of domestic semiconductors in the past, while not forgetting to look at the cutting-edge technology of starry sky research.