Recently at the IEEE Electronic Devices Conference (IEDM), engineers from TSMC, the University of California, San Diego, and Stanford University introduced a new manufacturing process that can better control the deposition of high-K dielectrics in carbon nanotransistors. This control is important for ensuring transistors It is vital to shut down completely when needed.
Simply put, the research team invented a new process for manufacturing gate dielectrics. The gate dielectric is an insulating layer between the gate electrode and the channel region of the transistor. During operation, the voltage at the gate creates an electric field in the channel region to cut off the current.
In recent years, people’s interest in carbon nano-transistors has increased. The main reason is that they may be smaller than silicon transistors and provide a way to make multilayer circuits easier than silicon transistors. Thanks to a series of developments, today's carbon nanotubes are gradually approaching the functions of silicon.
But for decades, as the size of silicon transistors shrinks, insulating layers made of silicon dioxide must become thinner and thinner in order to control current with less voltage, thereby reducing energy consumption. Eventually, the insulating barrier becomes very thin, so thin that electric charges can pass through it, causing current leakage and wasting energy.
Therefore, how to solve the problems of transistor leakage and energy waste is also an important direction that the industry has been studying.
1. The previous new hafnium dioxide dielectric materials still have problems
More than ten years ago, the silicon semiconductor industry solved this problem by switching to a new dielectric material-hafnium dioxide (HfO2).
Compared with silicon dioxide, hafnium dioxide has a higher dielectric constant (High-K), which means that a relatively thick high-K dielectric layer is electrically equivalent to a very thin silicon oxide layer.
Although researchers hope to use hafnium dioxide to form gate dielectrics in carbon nanotube transistors, one problem with carbon nanotubes is that they cannot form high-K dielectrics in the thin layers required for scaled-down devices.
How is a high-K dielectric formed? Its deposition method is called atomic layer deposition. As the name suggests, it is an oxide layer formed naturally on the surface of silicon, as thin as an atom. But it can only build one atomic layer at a time and needs a "pedestal" that can form a deposit.
However, since both carbon dioxide and carbon monoxide are gases, carbon nanotubes do not have a "foothold" for deposition and cannot form an oxide layer naturally. At the same time, any defects in the nanotubes that may cause the required "dangling bonds" will limit their ability to conduct current.
A dangling bond is a kind of chemical bond. Generally, the crystal lattice suddenly terminates at the surface. Each atom in the outermost layer of the surface will have an unpaired electron, that is, an unsaturated bond. This bond is called a dangling bond. .
2. A new solution for the formation of high-K dielectric: the combination of hafnium dioxide and alumina
"The formation of high-K dielectrics has always been a big problem." said Hansen Huang, chief scientist at TSMC and a professor at Stanford University. Basically, oxide thicker than nanotubes must be poured on top of nanotubes, rather than in smaller transistors.
He believes that if you want to figure out why this problem occurs, you can imagine the effect of the grid voltage as stepping on a garden pipe with your foot, trying to prevent water from flowing through the pipe, but if you put a pile between your feet and the pipe Pillow (like a thick oxide), it becomes more difficult to stop water from passing through.
Matthias Passlack of TSMC and Professor Andrew Kummel of the University of California, San Diego proposed a solution that combines the atomic layer deposition of hafnium dioxide with aluminum oxide (Al2O3), the dielectric constant material in the deposition.
Alumina is deposited using the nano-mist process invented by the University of California, San Diego. Like water vapor condensing to form a mist, aluminum oxide is condensed into clusters to cover the surface of the nanotubes, so that the hafnium dioxide can use the surface dielectric as a foothold to begin atomic layer deposition.
The comprehensive electrical properties of these two dielectrics allowed the team to fabricate a gate dielectric with a thickness of less than 4nm under a gate with a width of only 15nm. The resulting device has similar I/O current characteristics to silicon CMOS devices. Simultaneous simulation shows that even small devices with thinner gate dielectrics can work normally.
3. Carbon nanotubes still have a certain distance beyond silicon transistors
But before carbon nanotube devices can be comparable to silicon transistors, much work needs to be done. Currently, although some problems have been resolved, they have not yet been integrated into a single device.
For example, the single nanotube in the device proposed by Huang Hansen limits the current that the transistor can drive. He also mentioned that it has always been a challenge to align multiple identical nanotubes perfectly.
But recently, researchers in the laboratory of Professor Peng Lianmao of Peking University have successfully used technology to arrange 250 carbon nanotubes per micrometer, which means that corresponding solutions may soon appear.
Another problem is the resistance between the metal electrodes of the device and the carbon nanotubes, especially when the size of these contacts is reduced to the size currently used in advanced silicon chips.
Last year, Professor Huang Hansen’s student Greg Pitner (now a TSMC researcher and lead author of the IEDM study) reported a method that can reduce the resistance of one contact type (P-type) to less than twice the theoretical limit of 10nm contact.
However, the N-type contacts of carbon nanotubes have not yet reached a similar level of performance, and CMOS logic chips also include two types.
Another problem is the need to dope carbon nanotubes to increase the number of carriers on both sides of the gate, mainly in silicon by replacing some atoms in the crystal lattice with other elements.
But this is not feasible in carbon nanotubes, because it destroys the electronic capabilities of the structure. In contrast, carbon nanotube transistors use electrostatic doping. In this case, the cost of the dielectric layer will be deliberately manipulated to extract electrons or provide electrons to the nanotubes.
Hansen Huang mentioned that his former student, Rebecca Park, used molybdenum oxide in this layer to achieve good results.
Conclusion: A long way to go for semiconductor transistor innovation
With the gradual slowdown of Moore's Law in recent years, the industry has been trying to explore the possibility of further innovation and development of transistors from different directions such as materials, packaging, and technology.
However, it seems that although each research direction has made certain progress, their feasibility is still far away from the real landing. How to better combine these innovations to develop technologies beyond silicon, researchers still have a long way to go.